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| United States Patent | 4,841,573 |
| Fujita | June 20, 1989 |
A stereophonic signal processing circuit is designed to be provided with a pair of level compression circuits compressing peak levels of a pair of stereophonic input signals into 1/2 power each, an arithmetic mean circuit determining an arithmetic mean between a pair of output signals issued from the level compression circuits, and a level expansion circuit expanding a peak level of an output signal from the arithmetic mean circuit into the 2nd power of the level so that an output signal from the level expansion circuit is reproduced midway between individual reproducing positions of the pair of stereophonic input signals. A delay circuit may be connected between the arithmetic mean circuit and the level expansion circuit. The stereophonic signal processing circuit makes it possible to cause more fully the lateralization of a reproduced sound and can be fabricated at a low cost.
| Inventors: | Fujita; Shinichi (Hamamatsu, JP) |
|---|---|
| Assignee: |
Yamaha Corporation
(Hamamatsu,
JP)
|
| Family ID: | 16705544 |
| Appl. No.: | 07/237,986 |
| Filed: | August 29, 1988 |
| Aug 31, 1987 [JP] | 62-217521 | |||
| Current U.S. Class: | 381/27; 381/106 |
| Current CPC Class: | H04S 5/00 (20130101); H04S 5/02 (20130101); H04S 2400/05 (20130101) |
| Current International Class: | H04S 5/00 (20060101); H04S 5/02 (20060101); H04S 3/00 (20060101); H04S 003/00 () |
| Field of Search: | ;381/17,18,19,22,24,27,106,1 ;333/14 |
| 3952157 | April 1976 | Takahashi et al. |
| 4392019 | July 1983 | Halliday |
| 4685136 | August 1987 | Latshaw |
| 4736434 | April 1985 | Filliman |
| 4747142 | May 1988 | Tofte |
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